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Pull requests: diffblue/hw-cbmc

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Pull requests list

Verilog: create the transition relation from the RTL representation Verilog
#2119 opened Aug 27, 2026 by kroening Collaborator Loading…
Verilog: fix upper bound when printing extractbits expressions Verilog
#2118 opened Aug 21, 2026 by kroening Collaborator Loading…
1
Verilog: register-transfer level IR layer Verilog
#2117 opened Aug 21, 2026 by kroening Collaborator Loading…
Verilog: resolve function calls in generate/named block scopes Verilog
#2116 opened Aug 21, 2026 by kroening Collaborator • Draft
Verilog: import of tasks/functions in interfaces and modports Verilog
#2115 opened Aug 21, 2026 by kroening Collaborator • Draft
Verilog: hierarchical references into named generate blocks Verilog
#2101 opened Aug 12, 2026 by kroening Collaborator • Draft
Verilog: assignments between unpacked arrays of equivalent types Verilog
#2100 opened Aug 12, 2026 by kroening Collaborator • Draft
Verilog: simulation time system functions Verilog
#2092 opened Aug 12, 2026 by kroening Collaborator • Draft
Verilog: loop-local genvar scoping Verilog
#2091 opened Aug 12, 2026 by kroening Collaborator • Draft
2
Verilog: fix the constant-expression interpreter for the conditional operator and zero-width replication Verilog
#2090 opened Aug 12, 2026 by kroening Collaborator • Draft
1
Verilog: parse packages before the files that import them Verilog
#2082 opened Aug 11, 2026 by kroening Collaborator • Draft
Verilog: allow interface, package and class names as named formals Verilog
#2080 opened Aug 11, 2026 by kroening Collaborator • Draft
Verilog: arrays of interface ports Verilog
#2079 opened Aug 11, 2026 by kroening Collaborator • Draft
1
New IC3: extract blocking phase engines
#2072 opened Aug 9, 2026 by kroening Collaborator • Draft
New IC3: factor solver initialization engines
#2071 opened Aug 9, 2026 by kroening Collaborator • Draft
New IC3: extract property driver helpers engines
#2070 opened Aug 9, 2026 by kroening Collaborator • Draft
Verilog: support package export declarations Verilog
#2069 opened Aug 9, 2026 by kroening Collaborator • Draft
Verilog: preserve genvars while elaborating module instances Verilog
#2067 opened Aug 9, 2026 by kroening Collaborator Loading…
New IC3: compare SAT backends on HWMCC17 engines
#2066 opened Aug 9, 2026 by kroening Collaborator • Draft
Do not review
#2064 opened Aug 9, 2026 by kroening Collaborator • Draft
extract verilog_set_genvarst::build_map() cleanup Verilog
#2063 opened Aug 5, 2026 by kroening Collaborator Loading…
1
Verilog: accept struct/array/union as constant expressions Verilog
#2059 opened Aug 1, 2026 by kroening Collaborator Loading…
1
Verilog: fold Verilog-specific constructs when propagating constants in synthesis Verilog
#2053 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fix three type-checker gaps from LogikBench triage Verilog
#2052 opened Jul 23, 2026 by kroening Collaborator • Draft
1
Verilog: don't treat 'integer' loop counters as synthesis driver conflicts Verilog
#2049 opened Jul 23, 2026 by kroening Collaborator • Draft
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