test: add validated NAO cases to CUDA CI - #7856
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Summary
This PR adds validated GPU integration tests from
02_NAO_Gammaand03_NAO_multikto the existing CUDA CI workflow.The scope of this PR is intentionally limited to integrating cases that
currently pass on GPU. Cases that are known to fail or require unavailable
build features are excluded from
CASES_GPU.txtand will be handledseparately in follow-up issues / bug-fix PRs.
Changes
tests/02_NAO_Gamma/CASES_GPU.txttests/03_NAO_multik/CASES_GPU.txt.github/workflows/cuda.ymlto run both case lists on GPUdevice gpuat CI runtime only for cases included in the correspondingCASES_GPU.txtINPUTfileNo ABACUS source code, reference data, CPU test configuration, or failing
test cases are modified in this PR.
GPU validation
Local GPU validation was performed on an NVIDIA GeForce RTX 4090 using a
candidate patch based on commit:
0dca9dd7820bea3075e8e670f822269fb6732f18(
Fix: calculate net force after symmetrization (#7846))For the local GPU validation,
device gpuwas injected into the selectedcases'
INPUTfiles at runtime. The GPU build was executed through the localabacus_gpu_timeout.shwrapper.02_NAO_Gamma
The final
CASES_GPU.txtcase set exactly matches the set of directory-levelcases successfully exercised in the GPU validation run.
03_NAO_multik
The final
CASES_GPU.txtcase set exactly matches the set of directory-levelcases successfully exercised in the GPU validation run.
In total, this PR adds 88 validated NAO cases to the CUDA CI path.
The missing-
INPUTfail-fast guard was added after the GPU validation. Itdoes not change the execution path of the validated 88 cases because every
listed case currently contains an
INPUTfile.Cases intentionally excluded
02_NAO_Gamma
scf_FeBiTeks_solver = genelpais not supported for GPU acceleration.scf_metagga(
ENABLE_LIBXC=OFF).03_NAO_multik
scf_u_rampks_solver = genelpais not supported for GPU acceleration.scf_symm_precks_solver = genelpais not supported for GPU acceleration.scf_out_chg_tau(
ENABLE_LIBXC=OFF).relax_cell_vdw4_d4(
ENABLE_DFTD4=OFF).relax_cell_vdw4_d4s(
ENABLE_DFTD4=OFF).scf_out_hsr_spin4the CPU/reference result.
nscf_out_hsr_tr_rrthe CPU/reference result.
For the last two cases, CPU control runs complete successfully and reproduce
the repository references, while GPU runs retain additional near-zero entries
and therefore modify the CSR sparsity structure. The exact source-level cause
is intentionally not addressed in this PR.
Scope
This PR only establishes CUDA CI coverage for currently validated
02_NAO_Gammaand03_NAO_multikcases.It intentionally does not:
ks_solverbehavior;Those issues will be handled separately so that each PR has one focused
objective.