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Merged
alexcrichton merged 1 commit into from
Jul 23, 2026
Merged

winch(aarch64): v128 min, max, and avgr ops #13939

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45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_avgr_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.avgr_u (v128.const i16x8 1 2 0xFFFF 0xFFFF 0 1 0x8000 0x7FFF) (v128.const i16x8 1 2 0xFFFF 0xFFFF 0 1 0x8000 0x7FFF)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; urhadd v1.8h, v1.8h, v0.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x01, 0x00, 0x02, 0x00
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: .byte 0x00, 0x00, 0x01, 0x00
;; 8c: .byte 0x00, 0x80, 0xff, 0x7f
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_max_s.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.max_s (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; smax v1.8h, v0.8h, v1.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x80, 0xff, 0xff
;; 84: udf #1
;; 88: .byte 0x39, 0x30, 0xc7, 0xcf
;; 8c: .byte 0xff, 0x7f, 0xff, 0x00
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_max_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.max_u (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; umax v1.8h, v0.8h, v1.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x80, 0xff, 0xff
;; 84: udf #1
;; 88: .byte 0x39, 0x30, 0xc7, 0xcf
;; 8c: .byte 0xff, 0x7f, 0xff, 0x00
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_min_s.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.min_s (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; smin v1.8h, v0.8h, v1.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x80, 0xff, 0xff
;; 84: udf #1
;; 88: .byte 0x39, 0x30, 0xc7, 0xcf
;; 8c: .byte 0xff, 0x7f, 0xff, 0x00
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i16x8_min_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i16x8.min_u (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; umin v1.8h, v0.8h, v1.8h
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x80, 0xff, 0xff
;; 84: udf #1
;; 88: .byte 0x39, 0x30, 0xc7, 0xcf
;; 8c: .byte 0xff, 0x7f, 0xff, 0x00
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_max_s.wat
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@@ -0,0 +1,45 @@
;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.max_s (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; smax v1.4s, v0.4s, v1.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x00, 0x00, 0x80
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #1
;; 8c: udf #0
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_max_u.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.max_u (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; umax v1.4s, v0.4s, v1.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x00, 0x00, 0x80
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #1
;; 8c: udf #0
45 changes: 45 additions & 0 deletions tests/disas/winch/aarch64/v128_ops/i32x4_min_s.wat
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;;! target = "aarch64"
;;! test = "winch"

(module
(memory 1)
(func (export "run")
(v128.store (i32.const 0)
(i32x4.min_s (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0)))))
;; wasm[0]::function[0]:
;; stp x29, x30, [sp, #-0x10]!
;; mov x29, sp
;; str x28, [sp, #-0x10]!
;; mov x28, sp
;; ldur x16, [x0, #8]
;; ldur x16, [x16, #0x18]
;; mov x17, #0
;; movk x17, #0x10
;; add x16, x16, x17
;; cmp sp, x16
;; b.lo #0x74
;; 2c: mov x9, x0
;; sub x28, x28, #0x10
;; mov sp, x28
;; stur x0, [x28, #8]
;; stur x1, [x28]
;; ldr q0, #0x80
;; ldr q1, #0x80
;; smin v1.4s, v0.4s, v1.4s
;; mov x0, #0
;; ldur x1, [x9, #0x38]
;; add x1, x1, w0, uxtw
;; stur q1, [x1]
;; add x28, x28, #0x10
;; mov sp, x28
;; mov sp, x28
;; ldr x28, [sp], #0x10
;; ldp x29, x30, [sp], #0x10
;; ret
;; 74: udf #0xc11f
;; 78: udf #0
;; 7c: udf #0
;; 80: .byte 0x00, 0x00, 0x00, 0x80
;; 84: .byte 0xff, 0xff, 0xff, 0xff
;; 88: udf #1
;; 8c: udf #0
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