riscv: Fix privileged trap controls

[whensun]

This PR fixes RISC-V privileged trap control behavior in tlib.

It allows mstatus.TVM, TW, and TSR to be written when S-mode is supported, fixes their bit definitions, and makes SFENCE.VMA trap when executed from U-mode or when TVM blocks it in S-mode.

Related to renode/renode#908
Related to renode/renode#926

[FW-Nagorko]

Thank you for your contribution.
We have been able to verify that the sfence.vma instruction is incorrectly permitted in u-mode and we will be merging the fix.
When it comes to the flags in mstatus register, if we allow for them changing, it follows that they should have the expected side-effects. The TSR and TVM flags are easy enough to implement, and we will be adding support for that. The TW flag however is not so easy, as there is no built-in way to handle it fully in tlib. We will only limit the change to TVM and TSR for now.

[whensun]

Thank you for verifying the issues and for the explanation.

That makes sense. Limiting the current fix to TVM and TSR is reasonable, and TW can be handled separately in the future.