riscv: Mask mepc[0] and sepc[0] - #27
Conversation
|
Thank You for your contribution. We have been able to verify that the change to mask mepc[0] and sepc[0] is correct, and we will be merging it into the codebase. We would like to ask you to explain the reasoning behind masking out the |
|
Hello, thank you for your reply. I should clarify that my intention wasn't to claim that the entire Currently, tlib stores the full written value directly, so writing all ones makes every field read back as one. The RISC-V Privileged Architecture specification requires the following fields to be read-only zero when their related extensions are not implemented:
From my inspection, tlib does not appear to explicitly support these extensions.
I agree that using a zero mask for the entire register is too broad because it also clears unrelated fields such as
I will remove the current |
|
I have updated the PR. The |
|
Thank you for your contribution. We have merged your changes in c2885ef. |
tlib bug antmicro#27. The IEEE-754-2008 min/maxNum quiet-NaN shortcut in softfloat-2's MINMAX macro (floatN_maxnum/minnum) returns the non-NaN operand verbatim when the other operand is a quiet NaN, WITHOUT applying float_squash_input_denormal. The non-NaN float_max/float_min path already squashes both inputs, so only the NaN shortcut skipped it. Under FPSCR.FZ=1 that returned an un-flushed denormal (and never raised IDC/InputDenorm), diverging from the ARM ARM (DDI 0403E.e): FPMaxNum(qNaN, x) substitutes the qNaN with -Infinity and calls FPMax, whose FPUnpack flushes x's denormal to a signed zero and raises IDC. Fix: squash both operands at the top of maxnum/minnum (mirroring float_minmax). squash_input_denormal is a no-op unless FZ is set, so non-FZ behavior and other targets are unchanged. Found by pyrite's rn-cpu VMAXNM/VMINNM differential fuzzer (VMAXNM.F32(qNaN, +denormal), FZ=1: tlib kept the raw denormal, rn-cpu's spec-first FPMaxNum yielded +0.0 with IDC). rn-cpu is not bent to the omission; repro asserts the SPEC in crates/rn-cpu/tests/tlib_bug_repro.rs.
3 participants
This PR fixes RISC-V CSR field masking in tlib.
It masks mepc[0] and sepc[0], which are architecturally hardwired to zero.
Related to renode/renode#905
Related to renode/renode#906