feat(fpga_diff): add UVHS NutShell trace DDR - #152
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- select XSTop and standalone memory ports when NO_DIFF=1 - omit DiffTest, XDMA IP, and PCIe constraints from standalone projects - keep DMA detection and JTAG programming shared with the normal flow
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- add UVHS IP export, frontend partitioning, backend, and runtime targets - constrain XiangShan/CMN placement, DDR, XDMA, IMSIC, clocks, and TDM - support generalBus flash/DDR access and detached hardware sessions - add KMH ILA probes, trigger control, and gated-clock capture - preserve Vivado, NO_DIFF, and RTL_INCLUDE file-list behavior Co-authored-by: Kamimiao <fengkehan@bosc.ac.cn>
Add the reusable Hejian UVHS FPGA DiffTest build/runtime flow, preserve NutShell integration, and support the board-validated single-FPGA XiangShan configuration at 25 MHz.
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This PR adds passive NutShell commit tracing to dedicated UVHS DDR channels.
The trace path does not backpressure or stall the CPU. When the ingress FIFO is full, the current trace record is dropped, and the embedded sequence number exposes the gap.
The three-FPGA topology is:
F2: NutShell CPU, XDMA, and trace DDR channel 0
F1: trace DDR channel 1
F3: functional workload DDR
Usage
Build the trace-enabled NutShell target with:
cd fpga_diff
make uvhs_hejian_pcie_x4_nutshell_trace_all
CORE_DIR=/path/to/NutShell
SUFFIX=
The generated project is located at:
fpga_diff_uvhs_nutshell-
This target requires usable DDR cards for F1, F2, and F3.
Run FPGA DiffTest through the normal UVHS flow. Workloads are still written to the functional DDR through H2C; no separate workload-loading flow is introduced.
Trace data can be read through the UVHS runtime:
readmem
-rtl fpga_top_debug.core_def.U_CPU_TRACE.U_CPU_TRACE_CH0_DDR
-start 0 -end
-file trace-ch0.hex -hex
readmem
-rtl fpga_top_debug.core_def.U_CPU_TRACE.U_CPU_TRACE_CH1_DDR
-start 0 -end
-file trace-ch1.hex -hex
The default NutShell and probe targets remain unchanged. Trace RTL is only included when building uvhs_hejian_pcie_x4_nutshell_trace_all.