feat: add FP8-K NVFP4-V KV cache support

[meenchen]

Description

Draft integration for an FP8-K / NVFP4-V paged KV cache in the PyTorch runtime.

• adds the mixed cache quantization mode and argument validation
• stores compact FP8 K plus packed NVFP4 V and V block scales
• routes separate K/V buffers and scale metadata to FlashInfer TRTLLM-Gen FMHA
• sizes the mixed cache correctly in the hybrid cache manager
• preserves CUDA-graph-stable cache views and counter buffers

Kernel dependencies:

• TRTLLM-Gen mixed-KV kernel change (internal dependency)
• FlashInfer draft branch: https://github.com/meenchen/flashinfer/tree/fp8-k-nvfp4-v-production

Validation

• rebased onto current TensorRT-LLM main
• Python syntax checks pass
• focused unit tests are included for quantization mode, page indexing, cache sizing, and hybrid cache allocation
• end-to-end consumer validation remains gated on publishing an ABI-coherent TRTLLM-Gen/FlashInfer cubin package

This is intentionally a draft until the kernel and package dependencies land.