Add digital IP blocks

[padhmanethrri]

Purpose

Added digital IP blocks developed using Verilog through the NgVeri feature of eSim, as part of the FOSSEE eSim Summer Fellowship 2026.

IPs Included

• CRC-8 Generator
• Elastic Buffer (CDC FIFO)
• Frequency Comparator
• Hamming Distance Accumulator
• LFSR
• Razor Flip-Flop
• Scan Chain Controller
• Sorter

Contribution Checklist

• One commit per IP
• IP name used as the commit message
• eSim test circuit project files included
• Verilog files included
• README.md included
• Block diagram included
• One PR raised for the intern