diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_avgr_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_avgr_u.wat new file mode 100644 index 000000000000..f89d56ada1f6 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_avgr_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.avgr_u (v128.const i16x8 1 2 0xFFFF 0xFFFF 0 1 0x8000 0x7FFF) (v128.const i16x8 1 2 0xFFFF 0xFFFF 0 1 0x8000 0x7FFF))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; urhadd v1.8h, v1.8h, v0.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x00, 0x02, 0x00 +;; 84: .byte 0xff, 0xff, 0xff, 0xff +;; 88: .byte 0x00, 0x00, 0x01, 0x00 +;; 8c: .byte 0x00, 0x80, 0xff, 0x7f diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_max_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_max_s.wat new file mode 100644 index 000000000000..cb2263acc9f1 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_max_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.max_s (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smax v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x80, 0xff, 0xff +;; 84: udf #1 +;; 88: .byte 0x39, 0x30, 0xc7, 0xcf +;; 8c: .byte 0xff, 0x7f, 0xff, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_max_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_max_u.wat new file mode 100644 index 000000000000..eb3f729478e8 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_max_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.max_u (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umax v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x80, 0xff, 0xff +;; 84: udf #1 +;; 88: .byte 0x39, 0x30, 0xc7, 0xcf +;; 8c: .byte 0xff, 0x7f, 0xff, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_min_s.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_min_s.wat new file mode 100644 index 000000000000..f176b5326327 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_min_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.min_s (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smin v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x80, 0xff, 0xff +;; 84: udf #1 +;; 88: .byte 0x39, 0x30, 0xc7, 0xcf +;; 8c: .byte 0xff, 0x7f, 0xff, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i16x8_min_u.wat b/tests/disas/winch/aarch64/v128_ops/i16x8_min_u.wat new file mode 100644 index 000000000000..04ce16e9c915 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i16x8_min_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i16x8.min_u (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255) (v128.const i16x8 0x8000 -1 1 0 12345 -12345 32767 255))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umin v1.8h, v0.8h, v1.8h +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x80, 0xff, 0xff +;; 84: udf #1 +;; 88: .byte 0x39, 0x30, 0xc7, 0xcf +;; 8c: .byte 0xff, 0x7f, 0xff, 0x00 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_max_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_max_s.wat new file mode 100644 index 000000000000..f64807d01e23 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_max_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.max_s (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smax v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x00, 0x80 +;; 84: .byte 0xff, 0xff, 0xff, 0xff +;; 88: udf #1 +;; 8c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_max_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_max_u.wat new file mode 100644 index 000000000000..bc9b20b9ccd3 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_max_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.max_u (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umax v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x00, 0x80 +;; 84: .byte 0xff, 0xff, 0xff, 0xff +;; 88: udf #1 +;; 8c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_min_s.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_min_s.wat new file mode 100644 index 000000000000..2a12ccf50264 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_min_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.min_s (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smin v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x00, 0x80 +;; 84: .byte 0xff, 0xff, 0xff, 0xff +;; 88: udf #1 +;; 8c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i32x4_min_u.wat b/tests/disas/winch/aarch64/v128_ops/i32x4_min_u.wat new file mode 100644 index 000000000000..38619091f150 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i32x4_min_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i32x4.min_u (v128.const i32x4 0x80000000 -1 1 0) (v128.const i32x4 0x80000000 -1 1 0))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umin v1.4s, v0.4s, v1.4s +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x00, 0x00, 0x00, 0x80 +;; 84: .byte 0xff, 0xff, 0xff, 0xff +;; 88: udf #1 +;; 8c: udf #0 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_avgr_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_avgr_u.wat new file mode 100644 index 000000000000..f3b3a3949d81 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_avgr_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.avgr_u (v128.const i8x16 1 2 255 255 0 1 128 127 3 4 5 6 7 8 9 10) (v128.const i8x16 1 2 255 255 0 1 128 127 3 4 5 6 7 8 9 10))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; urhadd v1.16b, v1.16b, v0.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x01, 0x02, 0xff, 0xff +;; 84: .byte 0x00, 0x01, 0x80, 0x7f +;; 88: .byte 0x03, 0x04, 0x05, 0x06 +;; 8c: and w7, w0, w9, lsl #2 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_max_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_max_s.wat new file mode 100644 index 000000000000..8c62e63b857d --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_max_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.max_s (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11) (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smax v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x80, 0xff, 0x01, 0x00 +;; 84: .byte 0x02, 0xfe, 0x7f, 0x03 +;; 88: .byte 0x04, 0x05, 0x06, 0x07 +;; 8c: add w8, w8, w10, lsl #2 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_max_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_max_u.wat new file mode 100644 index 000000000000..5d7e621b0c4f --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_max_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.max_u (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11) (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umax v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x80, 0xff, 0x01, 0x00 +;; 84: .byte 0x02, 0xfe, 0x7f, 0x03 +;; 88: .byte 0x04, 0x05, 0x06, 0x07 +;; 8c: add w8, w8, w10, lsl #2 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_min_s.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_min_s.wat new file mode 100644 index 000000000000..05681e77d192 --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_min_s.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.min_s (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11) (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; smin v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x80, 0xff, 0x01, 0x00 +;; 84: .byte 0x02, 0xfe, 0x7f, 0x03 +;; 88: .byte 0x04, 0x05, 0x06, 0x07 +;; 8c: add w8, w8, w10, lsl #2 diff --git a/tests/disas/winch/aarch64/v128_ops/i8x16_min_u.wat b/tests/disas/winch/aarch64/v128_ops/i8x16_min_u.wat new file mode 100644 index 000000000000..effb4ad5998e --- /dev/null +++ b/tests/disas/winch/aarch64/v128_ops/i8x16_min_u.wat @@ -0,0 +1,45 @@ +;;! target = "aarch64" +;;! test = "winch" + +(module + (memory 1) + (func (export "run") + (v128.store (i32.const 0) + (i8x16.min_u (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11) (v128.const i8x16 128 255 1 0 2 254 127 3 4 5 6 7 8 9 10 11))))) +;; wasm[0]::function[0]: +;; stp x29, x30, [sp, #-0x10]! +;; mov x29, sp +;; str x28, [sp, #-0x10]! +;; mov x28, sp +;; ldur x16, [x0, #8] +;; ldur x16, [x16, #0x18] +;; mov x17, #0 +;; movk x17, #0x10 +;; add x16, x16, x17 +;; cmp sp, x16 +;; b.lo #0x74 +;; 2c: mov x9, x0 +;; sub x28, x28, #0x10 +;; mov sp, x28 +;; stur x0, [x28, #8] +;; stur x1, [x28] +;; ldr q0, #0x80 +;; ldr q1, #0x80 +;; umin v1.16b, v0.16b, v1.16b +;; mov x0, #0 +;; ldur x1, [x9, #0x38] +;; add x1, x1, w0, uxtw +;; stur q1, [x1] +;; add x28, x28, #0x10 +;; mov sp, x28 +;; mov sp, x28 +;; ldr x28, [sp], #0x10 +;; ldp x29, x30, [sp], #0x10 +;; ret +;; 74: udf #0xc11f +;; 78: udf #0 +;; 7c: udf #0 +;; 80: .byte 0x80, 0xff, 0x01, 0x00 +;; 84: .byte 0x02, 0xfe, 0x7f, 0x03 +;; 88: .byte 0x04, 0x05, 0x06, 0x07 +;; 8c: add w8, w8, w10, lsl #2 diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs index b4e83b385b88..f062ac72779a 100644 --- a/winch/codegen/src/isa/aarch64/masm.rs +++ b/winch/codegen/src/isa/aarch64/masm.rs @@ -1591,22 +1591,46 @@ impl Masm for MacroAssembler { fn v128_min( &mut self, - _src1: Reg, - _src2: Reg, - _dst: WritableReg, - _kind: V128MinKind, + src1: Reg, + src2: Reg, + dst: WritableReg, + kind: V128MinKind, ) -> Result<()> { - Err(format_err!(CodeGenError::unimplemented_masm_instruction())) + let (op, size) = match kind { + V128MinKind::F32x4 | V128MinKind::F64x2 => { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + V128MinKind::I8x16S => (VecALUOp::Smin, VectorSize::Size8x16), + V128MinKind::I8x16U => (VecALUOp::Umin, VectorSize::Size8x16), + V128MinKind::I16x8S => (VecALUOp::Smin, VectorSize::Size16x8), + V128MinKind::I16x8U => (VecALUOp::Umin, VectorSize::Size16x8), + V128MinKind::I32x4S => (VecALUOp::Smin, VectorSize::Size32x4), + V128MinKind::I32x4U => (VecALUOp::Umin, VectorSize::Size32x4), + }; + self.asm.vec_rrr(op, src1, src2, dst, size); + Ok(()) } fn v128_max( &mut self, - _src1: Reg, - _src2: Reg, - _dst: WritableReg, - _kind: V128MaxKind, + src1: Reg, + src2: Reg, + dst: WritableReg, + kind: V128MaxKind, ) -> Result<()> { - Err(format_err!(CodeGenError::unimplemented_masm_instruction())) + let (op, size) = match kind { + V128MaxKind::F32x4 | V128MaxKind::F64x2 => { + bail!(CodeGenError::unimplemented_masm_instruction()) + } + V128MaxKind::I8x16S => (VecALUOp::Smax, VectorSize::Size8x16), + V128MaxKind::I8x16U => (VecALUOp::Umax, VectorSize::Size8x16), + V128MaxKind::I16x8S => (VecALUOp::Smax, VectorSize::Size16x8), + V128MaxKind::I16x8U => (VecALUOp::Umax, VectorSize::Size16x8), + V128MaxKind::I32x4S => (VecALUOp::Smax, VectorSize::Size32x4), + V128MaxKind::I32x4U => (VecALUOp::Umax, VectorSize::Size32x4), + }; + self.asm.vec_rrr(op, src1, src2, dst, size); + Ok(()) } fn v128_extmul( @@ -1634,14 +1658,15 @@ impl Masm for MacroAssembler { bail!(CodeGenError::unimplemented_masm_instruction()) } - fn v128_avgr( - &mut self, - _lhs: Reg, - _rhs: Reg, - _dst: WritableReg, - _size: OperandSize, - ) -> Result<()> { - bail!(CodeGenError::unimplemented_masm_instruction()) + fn v128_avgr(&mut self, lhs: Reg, rhs: Reg, dst: WritableReg, size: OperandSize) -> Result<()> { + self.asm.vec_rrr( + VecALUOp::Urhadd, + lhs, + rhs, + dst, + VectorSize::from_lane_size(size.into(), true), + ); + Ok(()) } fn v128_div(