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<!DOCTYPE HTML>
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<title>Edu4Chip</title>
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<a href="index.html" class="logo"><strong>Edu4Chip</strong> - Joint Education for Advanced Chip Design in Europe</a>
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<h1>Program and curriculum</h1>
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<h2>Overview</h2>
<p>
The <strong>Edu4Chip</strong> program is a two-year, cutting-edge Master's degree in <strong>advanced chip design</strong>, offered in partnership by the partner universities. It is designed to give you both theoretical knowledge and hands-on experience, the program's highlight is the <strong>Chip Design Tape-Out Project</strong>, where you will design, manufacture, and test your own chip. An opportunity you will not find in typical microelectronics programs.
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<h2>Content</h2>
<p>
The program offers a blend of theory and practice and covers four areas.
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<div class="features">
<article>
<span class="icon solid fa-book"></span>
<div class="content">
<h3>Foundations</h3>
<p>You will build a strong foundation in digital and analog design. Core courses introduce you to the principles of chip architecture, circuit design, and essential tools used in the industry.</p>
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<article>
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<h3>Front-end design</h3>
<p>You will dive deeper into front-end design topics, gaining advanced knowledge in areas like system-on-chip integration, verification techniques, and preparing for the chip design project.</p>
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<span class="icon solid fa-microchip"></span>
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<h3>Back-end design</h3>
<p>Specialized courses focus on back-end design and physical design. This is when you will begin working on the practical stages of the tape-out project, bringing your chip design to life.</p>
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<h3>Master's thesis</h3>
<p>The final stage is dedicated to your Master’s thesis, often in collaboration with industry partners. You'll finalize your tape-out project, and after manufacturing, test and evaluate your chip.</p>
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<h2>Flexibility and international exchange</h2>
<p>
Edu4Chip is all about <strong>flexibility</strong>. You can tailor your learning experience by choosing from a wide range of specialized courses at each partner university. <strong>Want to focus on digital design in one unversity, then dive into analog circuits in another?</strong> The program allows you to do just that. Student exchange opportunities make it easy to take advantage of each university’s strengths, ensuring you get the most out of your education.
</p>
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<h2>Implementation at the partner universities</h2>
<p>
Edu4Chip is implemented within the existing academic structures of the five partner universities. The common focus is advanced chip design and hands-on learning, while each university contributes its own areas of expertise. This gives students a clear local study path and access to complementary strengths across the consortium through mobility and shared activities.
</p>
<div class="posts">
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<div style="padding-bottom: 0.8em;"><img src="images/logo_TUM.jpg" alt="Technical University of Munich logo" style="height:60px;" /></div>
<h3>Technical University of Munich (TUM)</h3>
<p>Edu4Chip is implemented through the MSc in Microelectronics and Chip Design, with digital and analog/mixed-signal routes and a multi-stage practical chip-design sequence.</p>
<p><strong>Strengths:</strong> digital and analog/mixed-signal circuits, physical design, EDA and machine learning, hardware security, clocking, power management, and chip test and evaluation.</p>
<ul class="actions">
<li><a href="programs/tum.html" target="_blank" class="button">Visit TUM program page</a></li>
</ul>
</article>
<article>
<div style="padding-bottom: 0.8em;"><img src="images/logo_KTH.jpg" alt="KTH Royal Institute of Technology logo" style="height:60px;" /></div>
<h3>KTH Royal Institute of Technology</h3>
<p>Edu4Chip is integrated into the Embedded Systems MSc, particularly the Embedded Electronics track, with a strong focus on ASIC design and a complete tape-out experience.</p>
<p><strong>Strengths:</strong> ASIC and FPGA implementation, mixed analog/digital design, analog and RF integrated circuits, tape-out, measurement, and project-based chip design.</p>
<ul class="actions">
<li><a href="programs/kth.html" target="_blank" class="button">Visit KTH program page</a></li>
</ul>
</article>
<article>
<div style="padding-bottom: 0.8em;"><img src="images/logo_DTU.jpg" alt="Technical University of Denmark logo" style="height:60px;" /></div>
<h3>Technical University of Denmark (DTU)</h3>
<p>Edu4Chip is integrated into the MSc in Computer Science and Engineering, primarily within the Digital Systems specialization, while relevant courses remain open as electives to students across the programme.</p>
<p><strong>Strengths:</strong> computer architecture, digital systems, open-source chip design toolchain, VLSI and chip implementation, agile hardware design, verification, and test.</p>
<ul class="actions">
<li><a href="programs/dtu.html" target="_blank" class="button">Visit DTU program page</a></li>
</ul>
</article>
<article>
<div style="padding-bottom: 0.8em;"><img src="images/logo_TAU_h.jpg" alt="Tampere University logo" style="height:60px;" /></div>
<h3>Tampere University (TAU)</h3>
<p>Edu4Chip is part of the Master’s Programme in Computing Sciences and Electrical Engineering through the Advanced Studies in System-on-Chip Design.</p>
<p><strong>Strengths:</strong> digital SoC design, RTL and logic synthesis, high-level synthesis, SystemVerilog/UVM verification, system design, and ASIC implementation.</p>
<ul class="actions">
<li><a href="programs/tau.html" target="_blank" class="button">Visit TAU program page</a></li>
</ul>
</article>
<article>
<div style="padding-bottom: 0.8em;"><img src="images/logo_IMT_h.jpg" alt="Institut Mines-Télécom logo" style="height:60px;" /></div>
<h3>Institut Mines-Télécom (IMT)</h3>
<p>Edu4Chip is embedded in the ISMIN engineering curriculum and in the Advanced Master in Microelectronics Circuit Design, linking semiconductor fundamentals to circuit and system design.</p>
<p><strong>Strengths:</strong> semiconductor physics and devices, process and manufacturing, cleanroom fabrication, analog and digital design, FPGA prototyping, and low-power design.</p>
<ul class="actions">
<li><a href="programs/imt.html" target="_blank" class="button">Visit IMT program page</a></li>
</ul>
</article>
<article></article>
</div>
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<hr class="major" />
<h2>Course offering at the partner universities</h2>
<p>
The tables below provide a concise summary of the newly developed or updated courses described in the <a href="resources/Edu4Chip_Module_Descriptions.pdf" target="_blank"><strong>Module Descriptions document</strong></a>. Credits and a short description are included to make the course offering easy to scan and compare. For complete and current course information, please follow the individual university programme pages.
</p>
<h3 id="tum">Technical University of Munich (TUM)</h3>
<p>TUM implements Edu4Chip through a dedicated MSc in Microelectronics and Chip Design. The course offering covers both digital and analog/mixed-signal design and includes practical work from functional design to physical implementation and post-fabrication evaluation.</p>
<div class="table-wrapper">
<table class="alt">
<thead>
<tr>
<th>Course / module</th>
<th>ECTS</th>
<th>Short description</th>
</tr>
</thead>
<tbody>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4075925&pOrgNr=43787" target="_blank">Chip Design Test and Evaluation Laboratory Course</a></td>
<td>5</td>
<td>Bring-up and characterization of fabricated chips, including test control, measurement and comparison against specifications.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=1744305&pOrgNr=14188" target="_blank">Circuit Design for Security</a></td>
<td>5</td>
<td>Digital circuit design in a hardware-security context, including security-oriented components and implementation considerations.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4075922&pOrgNr=14188" target="_blank">Design of Digital Circuits</a></td>
<td>5</td>
<td>Digital IC design principles with emphasis on circuit timing, power behavior and implementation trade-offs.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4038729&pOrgNr=53599" target="_blank">Fundamentals of CMOS Technology for Analog Design and Standard Cell Libraries</a></td>
<td>6</td>
<td>CMOS technology, MOSFET operation, variability and standard-cell design from analog and digital perspectives.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4092842&pOrgNr=15393" target="_blank">HDL Chip Design Laboratory</a></td>
<td>5</td>
<td>Hands-on HDL design and integration of an electronic system with processor, bus, peripherals and hardware accelerator.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4076378&pOrgNr=52577" target="_blank">Lab Analog Chip Design</a></td>
<td>5</td>
<td>Cadence-based analog IC design covering transistor biasing, amplifiers, current mirrors, OTAs and verification.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4040199&pOrgNr=53599" target="_blank">Logic Synthesis and Physical Design</a></td>
<td>6</td>
<td>Algorithms and tools for logic synthesis, placement, routing and optimization in the digital back-end flow.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4040185&pOrgNr=53599" target="_blank">Machine Learning for Electronic Design Automation and Manufacturing</a></td>
<td>5</td>
<td>Machine-learning methods applied to electronic design automation and semiconductor manufacturing problems.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4033744&pOrgNr=53600" target="_blank">Phase Locked Loop/Clocked Circuits</a></td>
<td>5</td>
<td>Clocked circuits, oscillators, clock generation and multiplication, PLL modelling, noise and system aspects.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4512214&pOrgNr=53600" target="_blank">Power Management Integrated Circuits</a></td>
<td>5</td>
<td>Power-management IC architectures, regulators and converters, efficiency, control and design trade-offs.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4075940&pOrgNr=43787" target="_blank">Research Laboratory Functional Design of Integrated Analog and Mixed-Signal Circuits</a></td>
<td>10</td>
<td>Group project developing a transistor-level analog/mixed-signal circuit from specification toward tape-out.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4075932&pOrgNr=43787" target="_blank">Research Laboratory Functional Design of Integrated Digital Circuits</a></td>
<td>10</td>
<td>Group project progressing from algorithm/specification to RTL and gate-level implementation of a digital circuit.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4101109&pOrgNr=43787" target="_blank">Research Laboratory Physical Design of Integrated Analog and Mixed-Signal Circuits</a></td>
<td>5</td>
<td>Back-end implementation from schematic to tape-out-capable GDSII, including layout, verification and sign-off.</td>
</tr>
<tr>
<td><a href="https://campus.tum.de/tumonline/WBMODHB.wbShowMHBReadOnly?pKnotenNr=4101108&pOrgNr=43787" target="_blank">Research Laboratory Physical Design of Integrated Digital Circuits</a></td>
<td>5</td>
<td>Digital physical design from gate netlist through floorplanning, place-and-route, clocking, closure and sign-off.</td>
</tr>
</tbody>
</table>
</div>
<ul class="actions">
<li><a href="programs/tum.html" target="_blank" class="button">Visit TUM program page</a></li>
<li><a href="https://www.cit.tum.de/fileadmin/w00byx/cit/Studium/Studiengaenge/Master_Microelectronics_and_Chip_Design/Module_handbook_Degree_Program_M.Sc._Microelectronics_and_Chip_Design.pdf" target="_blank" class="button">Full module handbook</a></li>
</ul>
<h3 id="kth">KTH Royal Institute of Technology</h3>
<p>KTH’s Embedded Electronics track is organized around a full ASIC experience. Foundational digital and analog IC courses prepare students for the 15 ECTS project course, where designs progress from specification to GDSII and selected chips are fabricated.</p>
<div class="table-wrapper">
<table class="alt">
<thead>
<tr>
<th>Course / module</th>
<th>ECTS</th>
<th>Short description</th>
</tr>
</thead>
<tbody>
<tr>
<td>Introduction Integrated Circuits</td>
<td>7.5</td>
<td>CMOS technology, hierarchical IC design, circuit simulation, physical implementation, verification and EDA tools.</td>
</tr>
<tr>
<td>Embedded Hardware Design in ASIC and FPGA</td>
<td>7.5</td>
<td>RTL and algorithm implementation in ASIC/FPGA using automated design flows, timing-aware design and verification.</td>
</tr>
<tr>
<td>Analog Integrated Circuits</td>
<td>7.5</td>
<td>Analog IC analysis and design with emphasis on feedback amplifiers and fundamental analog building blocks.</td>
</tr>
<tr>
<td>Design of radio frequency integrated circuits</td>
<td>7.5</td>
<td>RF design concepts, transceiver architectures and integrated building blocks for wireless systems.</td>
</tr>
<tr>
<td>Project Course in Application Specific Integrated Circuits</td>
<td>15</td>
<td>Full project-based ASIC flow from specification to GDSII tape-out; selected designs are fabricated and evaluated.</td>
</tr>
</tbody>
</table>
</div>
<ul class="actions">
<li><a href="programs/kth.html" target="_blank" class="button">Visit KTH program page</a></li>
</ul>
<h3 id="dtu">Technical University of Denmark (DTU)</h3>
<p>DTU integrates Edu4Chip into a flexible MSc structure rather than a mandatory fixed track. The courses below form the project-supported chip-design offering and together support a multi-semester, project-based path from architecture and RTL design to implementation, verification and test.</p>
<div class="table-wrapper">
<table class="alt">
<thead>
<tr>
<th>Course / module</th>
<th>ECTS</th>
<th>Short description</th>
</tr>
</thead>
<tbody>
<tr>
<td><a href="https://kurser.dtu.dk/course/02155" target="_blank">Computer Architecture and Engineering</a></td>
<td>5</td>
<td>Processor organization, ISA, pipelining, memory hierarchy, HW/SW interaction and performance optimization.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02214" target="_blank">Hardware/Software Codesign</a></td>
<td>5</td>
<td>SoC/MPSoC codesign, design-space exploration, high-level synthesis and hardware/software trade-offs.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02211" target="_blank">Research Topics in Computer Architecture</a></td>
<td>5</td>
<td>Advanced architecture topics combined with literature study and a group research-oriented hardware or software project.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02203" target="_blank">Design of Digital Systems</a></td>
<td>5</td>
<td>Systematic RTL design of large digital circuits, FPGA/chip implementation, and timing and area optimization.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02118" target="_blank">Introduction to Chip Design</a></td>
<td>5</td>
<td>Digital IC design with open-source design flows and hands-on virtual and physical tape-out activities.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02205" target="_blank">VLSI Design</a></td>
<td>5</td>
<td>MOS technology, ASIC/SoC design flows, synthesis, physical design, timing, power and low-power techniques.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02201" target="_blank">Agile Hardware Design</a></td>
<td>5</td>
<td>Chisel-based agile hardware development with reusable generators, abstraction and test-driven design.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02207" target="_blank">Verification of Digital Systems</a></td>
<td>5</td>
<td>Coverage-driven constrained-random verification, verification planning, testbenches and functional coverage.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02209" target="_blank">Test of Digital Systems</a></td>
<td>5</td>
<td>Fault models, test generation and design-for-test methods for reliable testing of digital circuits.</td>
</tr>
<tr>
<td><a href="https://kurser.dtu.dk/course/02225" target="_blank">Distributed Real-Time Systems</a><sup>1</sup></td>
<td>5</td>
<td>Real-time task models, schedulability analysis, time-sensitive networking, scheduling, and optimization of distributed real-time systems.</td>
</tr>
</tbody>
</table>
<p style="font-size: 0.85em; margin-top: 0.5em;">
<sup>1</sup> This course was added to the Edu4Chip offering after the Module Descriptions document was finalized.
</p>
</div>
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<h3 id="tau">Tampere University (TAU)</h3>
<p>TAU implements Edu4Chip as an Advanced Studies module in System-on-Chip Design. The course offering moves from digital design and synthesis to SoC design and verification, then to system design and chip implementation. Several courses are connected through a common chip-design project.</p>
<div class="table-wrapper">
<table class="alt">
<thead>
<tr>
<th>Course / module</th>
<th>ECTS</th>
<th>Short description</th>
</tr>
</thead>
<tbody>
<tr>
<td>Digital Design</td>
<td>5</td>
<td>Synchronous digital logic, RTL, state machines, timing analysis and FPGA design methods.</td>
</tr>
<tr>
<td>Logic Synthesis</td>
<td>5</td>
<td>VHDL RTL synthesis, simulation, multi-clock systems, synchronization and digital implementation flow.</td>
</tr>
<tr>
<td>System-on-Chip Design</td>
<td>5</td>
<td>SoC structures, interconnects and interfaces, SystemVerilog, IP-XACT and power/performance/area considerations.</td>
</tr>
<tr>
<td>High-level Synthesis</td>
<td>5</td>
<td>High-level synthesis, scheduling, memory architecture, pipelining and hardware-oriented coding techniques.</td>
</tr>
<tr>
<td>System Design</td>
<td>5</td>
<td>Embedded MPSoC technologies, model-based system design, HW/SW reuse and application portability.</td>
</tr>
<tr>
<td>System-on-Chip Verification</td>
<td>5</td>
<td>SoC verification, SystemVerilog object orientation, UVM, integration-level verification and formal methods.</td>
</tr>
<tr>
<td>Chip Implementation</td>
<td>5</td>
<td>ASIC synthesis and physical design, standard-cell libraries, chip I/O planning and sign-off tools.</td>
</tr>
</tbody>
</table>
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<h3 id="imt">Institut Mines-Télécom (IMT)</h3>
<p>IMT combines device- and process-level microelectronics with circuit and system design. The offering connects semiconductor fundamentals and fabrication with analog/digital design, processor architecture, synthesis, verification, FPGA prototyping and low-power techniques.</p>
<div class="table-wrapper">
<table class="alt">
<thead>
<tr>
<th>Course / module</th>
<th>ECTS</th>
<th>Short description</th>
</tr>
</thead>
<tbody>
<tr>
<td>Basics of Digital and Analog Electronics, Reminders</td>
<td>2</td>
<td>Core analog and digital electronics: AC/DC circuit analysis, Boolean logic, combinational and sequential design.</td>
</tr>
<tr>
<td>Semiconductor Physics</td>
<td>2</td>
<td>Semiconductor properties, energy bands, doping, carrier transport, generation and recombination.</td>
</tr>
<tr>
<td>Semiconductor Devices</td>
<td>3</td>
<td>Physical principles of microelectronic devices, including CMOS, FD-SOI and memory structures.</td>
</tr>
<tr>
<td>Process and Manufacturing</td>
<td>2</td>
<td>Cleanroom concepts and core fabrication steps including lithography, etching, implantation, deposition and oxidation.</td>
</tr>
<tr>
<td>Digital Design</td>
<td>4</td>
<td>CMOS digital circuits, timing and power, standard-cell design and Cadence-based layout, DRC and LVS.</td>
</tr>
<tr>
<td>Analog Design</td>
<td>4</td>
<td>Low-power analog IC design covering amplifiers, current mirrors, differential stages, op-amps and layout.</td>
</tr>
<tr>
<td>Processor Architecture</td>
<td>2</td>
<td>RISC-V processor architecture, pipelines, data/control dependencies and memory organization.</td>
</tr>
<tr>
<td>HDL Synthesis</td>
<td>4</td>
<td>SystemVerilog RTL modelling and synthesis methodology for the implementation of digital systems.</td>
</tr>
<tr>
<td>Advanced Simulation and Verification</td>
<td>3</td>
<td>Verification techniques including coverage, random testing and methods for checking circuit correctness during design.</td>
</tr>
<tr>
<td>Co-Design and FPGA Prototyping</td>
<td>3</td>
<td>Hardware/software partitioning and FPGA-based prototyping using a complete HW/SW design flow.</td>
</tr>
<tr>
<td>Low Power and Energy Harvesting</td>
<td>4</td>
<td>Low-power IC techniques together with system-level energy management and energy-harvesting concepts.</td>
</tr>
<tr>
<td>NMOS fabrication lab</td>
<td>4</td>
<td>One-week cleanroom laboratory covering NMOS fabrication, characterization, packaging and electrical testing.</td>
</tr>
</tbody>
</table>
</div>
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<!-- Break -->
<hr class="major" />
<h2>More detailed information</h2>
<p>
Each partner university (TUM, DTU, KTH, TAU, and IMT) implements the program slightly differently, adapting the structure and curriculum to fit their local context. Further details of the two-year Master's program in advanced chip design are available in the public documents below.
</p>
<h3> Program concept </h3>
<p>
This document presents the overall structure of the Edu4Chip Master’s program. It describes how the program is designed across partner universities, highlighting the strengths of each institution and the opportunities for student exchange.
</p>
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<li><a href="resources/Edu4Chip_The_Program_Concept.pdf" target="_blank" class="button">Read the deliverable</a></li>
</ul>
<h3>Curriculum of master programs and specializations</h3>
<p>
This document provides detailed information on the courses, teaching methods, and practical components such as lab work and chip tape-outs. It also includes mobility options and a catalogue of Lifelong Learning courses for professionals.
</p>
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<li><a href="resources/Edu4Chip_Curriculum_of_Master_Programs_and_Specializations_in_Edu4Chip.pdf" target="_blank" class="button">Read the deliverable</a></li>
</ul>
<h3>Module descriptions</h3>
<p>
This document provides an overview of the newly developed or updated courses in the Edu4Chip Master’s programs, presenting detailed course descriptions that complement the previous two documents "Program concept" and "Curriculum of master programs and specializations".
</p>
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</section>
<!-- END Descriptions -->
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